1. Field of the Invention
The present invention relates in general to an address input buffer circuit for a semi-conductor storage device, for inputting an address for selection of a specific location of the storage device, and more particularly to the address input buffer circuit having high speed and latching operation characteristics.
2. Description of the Prior Art
In all semi-conductor storage devices employing complementary MOS (CMOS) techniques, conventionally, there has necessarily been used an address input buffer circuit having an active region in which the voltage input high (VIH) of TTL potential is above 2.4 V and the voltage input low (VIL) thereof is below 0.8 V. More particularly, in a dynamic RAM (DRAM), there have been employed address input buffer circuits for X and Y-addresses. Herein, the address input buffer circuit for the X-address is believed to require a high speed, dynamic latching operation characteristic. Also, the address input buffer circuit for the Y-address is believed to require a static operation characteristic even in a low speed for realization of a successive column cycle, i.e., a fast page mode or a static column mode.
Referring to FIG. 1, there is shown a circuit diagram of a conventional address input buffer circuit employing logic gates. In this drawing, the conventional address input buffer circuit is shown to comprise an input circuit 11, a switching and latching circuit 12 and an output circuit 13.
The input circuit 11 is provided with an OR gate G1 including one input terminal for inputting an external input address signal An and the other input terminal for inputting an input enable signal .phi.E.
The switching and latching circuit 12 is provided with a switching circuit including p-channel MOSFETs MP1 and MP2 and n-channel MOSFETs MN1 and MN2, an inverter G6 for inputting an address interrupt signal .phi.AH, and inverters G2 and G3 for latch-functioning.
On the other hand, the output circuit 13 is provided with inverters G7 and G8, an AND gate G4 including one input terminal for inputting an output signal from the inverter G8 and the other input terminal for inputting an address output enable signal .phi.AE and an AND gate G5 including one input terminal for inputting the address output enable signal .phi.AE and the other input terminal for inputting an output signal from the inverter G7.
The operation of the conventional address input buffer circuit with the above-mentioned construction will now be mentioned with reference to FIG. 2 which is a waveform diagram of signals from respective components in FIG. 1.
Because the input enable signal .phi.E is high and the address output enable signal .phi.AE is low during the time period of t&lt;t1, the OR gate G1 outputs a high signal regardless of the other input state and the AND gates G4 and G5 each outputs a low signal regardless of the other input state.
If a drive input signal RAS to the dynamic RAM device is transited from a high state to a low state at instant t=t1, an active operation of the device is initiated and the input enable signal .phi.E is transited from the high state to a low state. As a result, the OR gate G1 outputs the transited state of the external input address signal An previously inputted at the other input terminal. The transited state of the external input address signal An is then transferred to a node 2, or an output stage of the switching circuit defined by the MOSFETs MP1 and MN1 each including its gate for inputting the inverted signal of the address interrupt signal .phi.AH, to a node 3 in a logic gate transfer manner and to nodes 6 and 7 in the output circuit 13. For example, supposing that the external input address signal An is high, signals at nodes 1, 2, 4 and 7 are maintained at a high state and signals at nodes 3 and 6 are maintained at a low state, while supposing that the external input address signal An is low, signals at nodes 1, 2, 4 and 7 are maintained at a low state and signals at nodes 3 and 6 are maintained at a high state.
If the address interrupt signal .phi.AH is transited from a low state to a high state at instant t=t2, a switch comprised of the MOSFETs MP2 and MN2 each including its gate for inputting the address interrupt signal .phi.AH is turned on, while a switch comprised of the MOSFETs MP1 and MN1 each including its gate for inputting the inverted signal of the address interrupt signal .phi.AH is turned off, thereby allowing an external input to the device and therefore an external noise thereto to be broken, and the node 2, or an input stage of the output circuit 13 to be latched by the inverters G2 and G3.
If the address output enable signal .phi.AE is transited from the low state to a high state at instant t=t3, the AND gates G4 and G5 are enabled and hence states of two internal address signals, or complement signals AXn and AXn are determined in accordance with a state of the external input address signal An.
However, although the above-mentioned conventional address input buffer circuit employing logic gates may embody a static operation by means of logic elements contained therein, there is a limit to its high speed realization due to delay time of the logic gates.
Referring to FIG. 3, there is shown a circuit diagram of another conventional address input buffer circuit utilizing cross-coupled flip-flops. This address input buffer circuit employs a sample and hold latching manner utilizing cross-coupled flip-flops for the purpose of the improvement in the above-mentioned problems with above conventional circuit. This address input buffer circuit has been adopted for 1M DRAM and 4M DRAM, each available from TOSHIBA Co., Ltd.
In FIG. 3, the conventional address input buffer circuit utilizing cross-coupled flip-flops is shown to comprise a pair of input circuits 36 and 37, a pair of setup circuits 31 and 33, a sense amplifying circuit 32 and an output circuit 38.
The input circuit 37 is provided with a n-channel MOSFET MNI1 including its gate for inputting an address input signal .phi.AI and its drain for inputting an external input address signal An. Also, the input circuit 36 is provided with a n-channel MOSFET MNI2 including its gate for inputting the address input signal .phi.AI and its drain for inputting an internal reference voltage signal Vref.
The setup circuit 31 is provided with series connected n-channel MOSFETs MNSU1 and MNSU2 for performing an address setup operation. Also, the setup circuit 33 is provided with series connected n-channel MOSFETs MNSU3 and MNSU4 for performing the address setup operation.
The sense amplifying circuit 32 includes cross-coupled p-channel MOSFETs MPS1 and MPS2 and cross-coupled n-channel MOSFETs MNS3 and MNS4.
The output circuit 38 is provided with a latching circuit 34 including a plurality of inverters G11 to G14, and an address reset circuit 35 including a pair of n-channel MOSFETs MNR1 and MNR2, each including its gate for inputting an address reset signal .phi.AR.
The internal reference voltage signal Vref represents a voltage generated for discrimination of an input level of a TTL potential in the device. For the purpose of the provision of the same margin for both of high and low voltages inputted to the device, the internal reference voltage signal Vref is usually maintained at the level of 1.6 V as defined by equation as follows: ##EQU1##
Now, the operation of the conventional address input buffer circuit utilizing cross-coupled flip-flops of the construction as mentioned above will be mentioned with reference to FIG. 4.
Referring to FIG. 4, there is shown a waveform diagram of signals from respective components in FIG. 3.
Because the address input signal .phi.AI and the address reset signal .phi.AR are high during the time period of t&lt;t11, the external input address signal An and the internal reference voltage signal Vref are transferred respectively to the setup circuits 31 and 33 respectively through the n-channel MOSFETs MNI1 and MNI2 and hence two internal address signals, or complement signals AXn and AXn are low in accordance with the high state of the address reset signal .phi.AR.
If an address setup signal .phi.AS is transited from a low state to a high state at instant t=t11, the setup circuit 31 including series connected n-channel MOSFETs MNSU1 and MNSU2 and the setup circuit 33 including series connected n-channel MOSFETs MNSU3 and MNSU4 operate such that potentials at both nodes 15 and 16 of the sense amplifying circuit 32 having been charged with source voltage Vcc are discharged respectively by the external input address signal An and the internal reference voltage signal Vref. As a result, there is generated a potential difference between the both nodes 15 and 16. Therefore, upon the enabling of the address setup signal .phi.AS, the external input address signal An is set up at the both nodes 15 and 16 of the sense amplifying circuit 32 by the setup circuits 31 and 33. If the address input signal .phi.AI is transited from the high state to a low state at instant t=t12, the n-channel MOSFETs MNI1 and MNI2 in the input circuits 37 and 36 are turned off, thereby allowing an external input to the device to be broken, and the sense amplifying circuit 32 to amplify the set up potential difference between the both nodes 15 and 16.
At this time, if the address reset signal .phi.AR is transited from the high state to a low state, address signals an and an outputted from the sense amplifying circuit 32 are transferred directly to the latching circuit 34 respectively through n-channel MOSFETs MN3 and MN4, with being placed respectively on the internal address signals AXn and AXn.
If a control signal .phi.AISO is transited from a high state to a low state at instant t=t13, the input address signals an and an are latched by the latching circuit 34 and the latched state of the address signals is maintained until the subsequent address reset.
FIG. 5 is a signal waveform diagram according to a result simulated with the conventional address input buffer circuit utilizing cross-coupled flip-flops.
However, the conventional address input buffer circuit utilizing cross-coupled flip-flops is difficult to realize a high speed operation in that it sets up the previously arrived address signals at the both nodes 15 and 16 of the sense amplifying circuit 32 by means of the setup circuits 31 and 33 during the time period of t11&lt;t&lt;t12 as shown in FIG. 5.
In addition, the discharging of potentials at the both nodes 15 and 16 having been charged with the source voltage Vcc induces indirectly the potential difference between the both nodes 15 and 16, thereby causing the potential difference to be lower than an actual potential difference between the external input address signal An and the internal reference voltage signal Vref.